Sample Vhdl Serial TX source code.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity SerialTx is
generic (BITS_PER_BAUD : integer := 11;
BITS_PER_BYTE : integer := 8;
BITS_PER_BAUD_M1 : integer := 10;
FOUR : integer := 4 );
port (-- Diagram Input Ports
TxDin : in unsigned (BITS_PER_BYTE-1 downto 0 );
TxDWr : in std_logic;
TxRst : in std_logic;
TxClk : in std_logic;
-- Diagram Output Ports
TxRdy : out std_logic;
TxD : out std_logic );
end entity SerialTx;
architecture Behavioral of SerialTx is
-- Object Output Declarations
signal Q_BaudCtr : unsigned (FOUR-1 downto 0 );
signal Qlsb_ShiftReg, Ytc_BaudCtr, Yparity_Parity1 : std_logic;
-- Object Input Declarations
signal MSBin_ShiftReg : std_logic ;
signal D_ShiftReg : unsigned (BITS_PER_BAUD_M1-1 downto 0 );
-- Local Variable Declarations
signal Q_ShiftReg : unsigned ( BITS_PER_BAUD_M1 -1 downto 0) ;
constant maxCount_BaudCtr : unsigned ( FOUR -1 downto 0) := to_unsigned (
BITS_PER_BAUD - 1, FOUR ) ;
constant ones_BaudCtr : unsigned ( FOUR -1 downto 0) := ( OTHERS =>'1') ;
constant zeros_BaudCtr : unsigned ( FOUR -1 downto 0) := ( OTHERS =>'0') ;
constant tcount_BaudCtr : unsigned ( FOUR -1 downto 0) := ( OTHERS =>'0') ;
-- Function Declarations
function rxor_Parity1 ( ina_Parity1 : unsigned ) return std_logic is
variable ret_Parity1 : std_logic ;
begin
for iterator in 0 to BITS_PER_BYTE -1 loop
if ( iterator = 0) then
ret_Parity1 := ina_Parity1 (0) ;
else
ret_Parity1 := ret_Parity1 XOR ina_Parity1 ( iterator ) ;
end if;
end loop ;
return ret_Parity1 ;
end function;
begin
-- Output Port Assignments
TxRdy <= Ytc_BaudCtr ;
TxD <= Qlsb_ShiftReg ;
-- Object Input Assignments
MSBin_ShiftReg <= '1' ;
D_ShiftReg <= Yparity_Parity1 & TxDin & '0' ;
--*****************************************************************************
-- Object:ShiftReg Class:ShiftRegister
--***************************** Tagged Values**********************************
-- WIDTH = 10 Edge = Rising Direction = Right
-- DataOut = Serial ShiftEn = UnUsed Clear = UnUsed
-- Set = Sync Load = Sync Rev = 1.07;
--*****************************************************************************
process ( TxClk )
begin
if rising_edge ( TxClk ) then
if ( TxRst ='1') then
Q_ShiftReg <= ( OTHERS =>'1') ;
elsif ( TxDWr ='1') then
Q_ShiftReg <= D_ShiftReg ;
else
Q_ShiftReg <= MSBin_ShiftReg & Q_ShiftReg ( BITS_PER_BAUD_M1 -1 downto 1) ;
end if;
end if;
end process;
Qlsb_ShiftReg <= Q_ShiftReg (0) ;
--*****************************************************************************
-- Object:BaudCtr Class:Counter
--***************************** Tagged Values**********************************
-- WIDTH = 4 MODULUS = 11 GrayOut = UnUsed
-- Edge = Rising Direction = Down CountEn = Used
-- Clear = Sync Set = UnUsed Load = UnUsed
-- TerminalCount = Comb Rev = 1.10;
--*****************************************************************************
process ( TxClk )
begin
if rising_edge ( TxClk ) then
if ( TxRst ='1') then
Q_BaudCtr <= ( OTHERS =>'0') ;
elsif ( not Ytc_BaudCtr or TxDWr) then
if ( Q_BaudCtr = zeros_BaudCtr ) then
Q_BaudCtr <= maxCount_BaudCtr ;
else
Q_BaudCtr <= Q_BaudCtr -1 ;
end if;
end if;
end if;
end process;
process ( Q_BaudCtr )
begin
if ( Q_BaudCtr = tcount_BaudCtr ) then
Ytc_BaudCtr <='1';
else
Ytc_BaudCtr <='0';
end if;
end process;
--*****************************************************************************
-- Object:Parity1 Class:Parity
--***************************** Tagged Values**********************************
-- WIDTH = 8 Function = Generator Parity = Odd
-- Registered = No Enable = UnUsed Rev = 1.07;
--*****************************************************************************
Yparity_Parity1 <= not rxor_Parity1 ( TxDin ) ;
end architecture;
Sample Vhdl Serial RX source code.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity SerialRx is
generic (ONE : integer := 1;
BITS_PER_BYTE : integer := 8;
THREE : integer := 3;
BITS_PER_BAUD_M1 : integer := 10 );
port (-- Diagram Input Ports
RxClkX8 : in std_logic;
RxD : in std_logic;
RxRst : in std_logic;
-- Diagram Output Ports
RxDoutValid : out std_logic;
FrameError : out std_logic;
RxDout : out unsigned (BITS_PER_BYTE-1 downto 0 );
ParError : out std_logic );
end entity SerialRx;
architecture Behavioral of SerialRx is
-- Object Output Declarations
signal Q_ShiftReg : unsigned (BITS_PER_BAUD_M1-1 downto 0 );
signal Q_BitSync : unsigned (THREE-1 downto 0 );
signal Qlsb_ShiftReg, Qtc_BitSync, Q_RxDReg, Yerror_Parity1 : std_logic;
-- Object Input Declarations
signal Dload_BitSync : unsigned (THREE-1 downto 0 );
signal SyncLoad_BitSync : std_logic ;
signal D_Parity1 : unsigned (BITS_PER_BYTE-1 downto 0 );
signal Parity_Parity1 : std_logic ;
-- Local Variable Declarations
constant tcount_BitSync : unsigned ( THREE -1 downto 0) := ( OTHERS =>'1') ;
-- Function Declarations
function rxor_Parity1 ( ina_Parity1 : unsigned ) return std_logic is
variable ret_Parity1 : std_logic ;
begin
for iterator in 0 to BITS_PER_BYTE -1 loop
if ( iterator = 0) then
ret_Parity1 := ina_Parity1 (0) ;
else
ret_Parity1 := ret_Parity1 XOR ina_Parity1 ( iterator ) ;
end if;
end loop ;
return ret_Parity1 ;
end function;
begin
-- Output Port Assignments
RxDoutValid <= not Q_ShiftReg(0) and Qtc_BitSync ;
FrameError <= not Q_RxDReg ;
RxDout <= Q_ShiftReg( 8 downto 1) ;
ParError <= Yerror_Parity1 ;
-- Object Input Assignments
Dload_BitSync <= B"110" ;
SyncLoad_BitSync <= Q_RxDReg xor RxD ;
D_Parity1 <= Q_ShiftReg( 8 downto 1) ;
Parity_Parity1 <= Q_ShiftReg(9) ;
--*****************************************************************************
-- Object:ShiftReg Class:ShiftRegister
--***************************** Tagged Values**********************************
-- WIDTH = 10 Edge = Rising Direction = Right
-- DataOut = Parallel ShiftEn = Used Clear = UnUsed
-- Set = Sync Load = UnUsed Rev = 1.07;
--*****************************************************************************
--Shift Reg with full baud - Low (space) at msb flags end of baud
process ( RxClkX8 )
begin
if rising_edge ( RxClkX8 ) then
if ( ( not Qlsb_ShiftReg and Qtc_BitSync ) or RxRst) then
Q_ShiftReg <= ( OTHERS =>'1') ;
elsif ( Qtc_BitSync ='1') then
Q_ShiftReg <= Q_RxDReg & Q_ShiftReg ( BITS_PER_BAUD_M1 -1 downto 1) ;
end if;
end if;
end process;
Qlsb_ShiftReg <= Q_ShiftReg (0) ; --
--*****************************************************************************
-- Object:BitSync Class:Counter
--***************************** Tagged Values**********************************
-- WIDTH = 3 MODULUS = UnUsed GrayOut = UnUsed
-- Edge = Rising Direction = Up CountEn = UnUsed
-- Clear = UnUsed Set = UnUsed Load = Sync
-- TerminalCount = Sync Rev = 1.10;
--*****************************************************************************
--TC flags center of bit cycle to clock data - Syncs on any RxD transition
process ( RxClkX8 )
begin
if rising_edge ( RxClkX8 ) then
if ( SyncLoad_BitSync ='1') then
Q_BitSync <= Dload_BitSync ;
if ( Dload_BitSync = tcount_BitSync ) then
Qtc_BitSync <='1';
else
Qtc_BitSync <='0';
end if;
else
Q_BitSync <= Q_BitSync +1 ;
if ( Q_BitSync = tcount_BitSync -1) then
Qtc_BitSync <='1';
else
Qtc_BitSync <='0';
end if;
end if;
end if;
end process; --
--*****************************************************************************
-- Object:RxDReg Class:Register
--***************************** Tagged Values**********************************
-- WIDTH = 1 Edge = Rising ClockEn = UnUsed
-- Clear = UnUsed Set = UnUsed Load = UnUsed
-- Rev = 1.02;
--*****************************************************************************
--Delays RxD by 1 RxClkX8 cycle
process ( RxClkX8 )
begin
if rising_edge ( RxClkX8 ) then
Q_RxDReg <= RxD ;
end if;
end process; --
--*****************************************************************************
-- Object:Parity1 Class:Parity
--***************************** Tagged Values**********************************
-- WIDTH = 8 Function = Checker Parity = Odd
-- Registered = No Enable = UnUsed Rev = 1.07;
--*****************************************************************************
Yerror_Parity1 <= not ( rxor_Parity1 ( D_Parity1 ) xor Parity_Parity1 ) ;
end architecture;