HDL Code Generation

The uml2hdl code generator has been carefully crafted to generate  HDL that is concise, easy to understand, and error-free.   
                       View Source Code Examples      

  • High Quality, Readable Code
    • Highly optimized
    • Easy to read and follow
    • No unnecessary or extraneous code.
    • Identifier names are automatically generated
      • Based on the Object's user-assigned name.
      • Can be overridden by assigning an alias.
  • VHDL or Verilog
    • Uml2hdl can generate  VHDL or Verilog HDL.
    • Change from VHDL to Verilog at the click of a button!
  • Validated UML Class Library
    • UML Classes provide basic HDL functions
      • Includes Counters, Registers, even LFSR's
    • Extensively verified
      • Ensures proper functionality of all configurations.
      • Object Verification Library (OVL) assertion based test benches are available upon request.

View Source Code Examples